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1 for more information www.linear.com/LT3668 typical a pplica t ion fea t ures descrip t ion 40v 400ma step-down switching regulator with dual fault protected tracking ldos the lt ? 3668 is a monolithic triple power supply composed of a 400 ma buck switching regulator and two 200 ma low dropout linear tracking regulators ( ldos).this provides a complete and robust power solution for applications that require the power supply of a sensor to tightly track the power supply of a measurement asic. each tracking ldo supplies 200 ma of output current with a typical dropout voltage of 340 mv, and each ldo has an accurate resistor programmable current limit. internal protection circuitry includes reverse- battery protection, current limiting, thermal limiting and reverse current protection. the buck regulator includes a high efficiency switch, a boost diode, and the necessary oscillator, control and logic circuitry. current mode topology is used for fast transient response and good loop stability. low ripple burst mode operation maintains high efficiency at low output currents while keeping output ripple below 15mv in a typical application. the LT3668 is available in a thermally-enhanced 16-lead msop package with exposed pad for low thermal resis - tance. no-load supply current a pplica t ions n dual low dropout linear tracking regulators 200ma outputs with programmable current limits 1.6 v to 45v input range fault protected to 45v n triple output supply from a single input requires only one inductor n i q = 50 a at 12v in to 6 v and 5 v with no load n buck regulator: low ripple (<15mv p-p ) burst mode operation ? 400ma output with internal power switch 4.3 v to 40v input operation range (60v max) n adjustable 250khz to 2.2mhz switching frequency n power good indicator n available in a thermally-enhanced 16-lead msop package n fault-protected sensor supply n automotive and industrial supplies n power for portable instrumentation l, lt , lt c , lt m , burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. input voltage (v) 5 0 supply current (a) 10 30 40 50 100 70 15 25 30 3668 ta01b 20 80 90 60 10 20 35 3668 ta01a en2/ilim2 en3/ilim3 gnd 5v 150ma 10f 10f in1 LT3668 boost sw da in3/bd in2 fb1 on off en pg rt adj2 out2 out3 adj3 4.7f 0.22f 22pf 27h 232k 6v 100ma 931k 294k 174k f = 600khz v in 7v to 40v transient to 60v 5v 150ma (follows out3) 22f LT3668 3668f
2 for more information www.linear.com/LT3668 adj 2, adj 3 voltage ................................................ 45 v out 2, out 3 voltage ............................................... 45v in 2 voltage ............................................................. 45 v out 2 C in 2 differential voltage .............................. 45v out 3 C in 3/ bd differential voltage ........................ 45v out 2 C adj 2 differential voltage ........................... 45v out 3 C adj 3 differential voltage ........................... 45v in 1, en voltage ( note 3) ........................................... 60 v in 1 reverse voltage ............................................... C 0.3 v en pin current ....................................................... C1 ma in 3/ bd voltage ......................................................... 30 v b oost pin voltage ................................................... 50 v b oost pin above sw pin ......................................... 30 v rt voltage .................................................................. 2 v fb 1 voltage ................................................................. 6 v en 2/ ilim 2, en 3/ ilim 3 voltage ................................... 4 v pg voltage ................................................................ 30 v o perating junction temperature range ( notes 4, 5) e -, i- grades ....................................... ? 40 c to 125 c storage temperature range .................. ? 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c (notes 1, 2) lead free finish tape and reel part marking package description temperature range LT3668emse#pbf LT3668emse#trpbf 3668 16-lead plastic msop C40c to 125c LT3668imse#pbf LT3668imse#trpbf 3668 16-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ p in c on f igura t ion a bsolu t e maxi m u m r a t ings 1 2 3 4 5 6 7 8 sw boost en rt in3/bd out3 adj3 fb1 16 15 14 13 12 11 10 9 da in1 pg en3/ilim3 en2/ilim2 in2 out2 adj2 top view 17 gnd mse package 16-lead plastic msop ja = 40c/w exposed pad ( pin 17) is gnd, must be soldered to pcb o r d er i n f or m a t ion LT3668 3668f
3 for more information www.linear.com/LT3668 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in1 = 12v unless otherwise noted. (note 4) parameter conditions min typ max units v in1 undervoltage lockout (note 6) v in2 = 0v, v in3/bd = 0v l 4 4.3 v v in1 overvoltage lockout l 40 42 44 v v in2 undervoltage lockout (note 6) v in1 = 3.5v, v in3/bd = 0v l 4 4.3 v quiescent current from in1 v en = 0.3v v en = 12v, v in2 = 0v, not switching l 0.01 13 1 30 a a quiescent current from in2 v en = 0.3v v en = 12v, v in1 = 0v, v in2 = 5v l 0.01 38 1 80 a a quiescent current from in1 + in2 v en = 0.3v, v in2 = 5v v en = 12v, v in2 = 5v, not switching l 0.01 40 1 90 a a quiescent current from in3/bd v en = 0.3v, v in3/bd = 5v v en = 12v, v in3/bd = 5v l 0.01 25 1 60 a a en pin current v en = 12v 0.6 2 a en input threshold 0.3 1.1 v power good pin pg leakage current v pg = 5v 0.1 1 a output voltage low i pg = 40a l 0.2 0.3 v threshold as % of v fb1 pin voltage falling pin voltage rising 88 108 90 110 92 112 % % pg threshold hysteresis measured at fb1 pin 30 mv switching regulator switching frequency r t = 37.4k r t = 102k r t = 487k l l l 1.8 0.8 220 2.0 0.94 243 2.1 1.1 300 mhz mhz khz minimum switch off-t ime l 120 190 ns switch current limit (note 7) 5% duty cycle, v in = 5v, v fb1 = 0v 90% duty cycle, v in = 5v, v fb1 = 0v l l 600 450 750 550 950 800 ma ma switch v cesat i sw = 200ma 300 mv da pin current to stop switching l 420 500 650 ma switch leakage current v sw = 0v 0.05 2 a boost schottky diode forward voltage i boostdiode = 50ma, v in = nc, v boost = 0v 900 mv boost schottky diode reverse leakage v reverse = 12v, v in = nc 0.04 4 a minimum boost voltage (note 8) l 1.7 2.5 v boost pin current i sw = 200ma, v boost = 15v 10 16 ma feedback voltage (fb1) l 1.188 1.176 1.2 1.2 1.212 1.224 v mv fb 1 pin bias current pin v oltage = 1.2v l 0.1 20 na reference voltage line regulation 4.2v < v in1 < 40v 0.001 0.005 %/v each ldo regulator minimum input voltage i load = 200ma l 1.6 2.2 v output voltage range l 1.1 10 v tracking error v out2/3 -v adj2/3 1.1v v adj2/3 5v, i load = 1ma 5v < v adj2/3 10v, i load = 1ma l l C6 C20 6 50 mv mv e lec t rical c harac t eris t ics LT3668 3668f
4 for more information www.linear.com/LT3668 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in1 = 12v unless otherwise noted. (note 4) parameter conditions min typ max units dropout voltage (notes 9, 10), v in = v out(nominal) i load = 1ma i load = 1ma l 70 165 210 mv mv i load = 50ma i load = 50ma l 230 300 400 mv mv i load = 100ma i load = 100ma l 280 400 450 mv mv i load = 200ma i load = 200ma l 340 650 700 mv mv gnd pin current, v in = v out(nominal) + 0.6v (notes 10, 11) i load = 0ma i load = 50ma i load = 200ma l l l 40 1 5 90 2 10 a ma ma quiescent current i in2 with ldo2 disabled quiescent current i in3/bd with ldo3 disabled v in1 = 0v, v in2 = 12v, v en2/ilim2 = 2v v in1 = 16v, v in3/bd = 12v, v en3/ilim3 = 2v 13 1.2 20 2 a a adj2 pin bias current (note 10) adj3 pin bias current (note 10) v adj2 10v, v adj2 v in2 C 0.6v, v out2 v in2 C 0.6v v adj3 10v, v adj3 v in3/bd C 0.6v, v out3 v in3/bd C 0.6v l l 600 600 na na ripple rejection v in C v out = 2v (avg), v ripple = 0.5v p-p , f ripple = 120hz, i load =200ma 60 85 db reverse output current (note 12) v out2 = 1.2v, v in1 = v in2 = v in3/bd = 0v v out3 = 1.2v, v in1 = v in2 = v in3/bd = 0v 5 5 40 40 a a input reverse leakage current ldo2 v in2 = C45v, v in1 = v in3/bd = v out2 = 0v l 300 a internal current limit v in2 = 2.2v, v out2 = 0v, en2/ilim2 pin grounded 300 ma ?v out2 = C5% l 220 ma v in3/bd = 2.2v, v out3 = 0v, en3/ilim3 pin grounded 300 ma ?v out3 = C5% l 220 ma externally programmed current limit r en/ilim = 31.6k, v out2/3 = 5v, v in2/3 5.6v r en/ilim = 6.19k, v out2/3 = 5v, v in2/3 5.6v r en/ilim = 6.19k, v out2/3 = 5v, 5.6v v in2/3 15v r en/ilim = 1.54k, v out2/3 = 5v, 5.6v v in2/3 15v l l l l 9.5 47 48.45 176 10 51 51 197 10.5 55 53.55 230 ma ma ma ma ldo en/ilim disable threshold 0.3 1.2 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: positive currents flow into pins, negative currents flow out of pins. minimum and maximum values refer to absolute values. note 3: absolute maximum voltage at the in1 and en pins is 60v for nonrepetitive 1 second transients, and 40v for continuous operation. note 4: the LT3668e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the ?40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT3668i is guaranteed over the full ?40c to 125c operating junction temperature range. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 6: this is the voltage necessary to keep the internal bias circuitry in regulation. note 7: current limit guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 8: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the switch. note 9: dropout voltage is the minimum input-to-output voltage differential needed for an ldo to maintain regulation at a specified output current. when an ldo is in dropout, its output voltage will be equal to v in C v drop . note 10: the LT3668 is tested and specified for these conditions with v adj2/3 = 5v. note 11: gnd pin current is tested with v in = v out(nominal) + 0.6v and a current source load. gnd pin current increases in dropout. note 12: reverse output current is tested with the in2 (in3/bd) pin grounded and the out2 (out3) pin forced to the rated output voltage. this current flows into the out2 (out3) pin and out of the gnd pin. LT3668 3668f
5 for more information www.linear.com/LT3668 typical p er f or m ance c harac t eris t ics no-load supply current no-load supply current maximum load current maximum load current switching regulator load regulation efficiency, v out1 = 3.3v efficiency, v out1 = 6v v fb1 vs temperature switch current limit t a = 25c, unless otherwise noted. temperature (c) ?50 1.10 v fb1 (v) 1.15 1.20 1.25 1.30 ?25 0 25 50 3668 g03 75 100 125 150 load current (ma) efficiency (%) 80 70 60 50 40 30 20 10 90 0.01 1 10 3668 g01 0 0.1 100 v in1 = 12v v in1 = 36v v in1 = 24v front page application buck regulator only v out1 = 3.3v l: mss7341-223mlb load current (ma) efficiency (%) 80 90 70 60 50 40 30 20 10 100 0.01 1 10 3668 g02 0 0.1 100 v in1 = 12v v in1 = 24v v in1 = 36v front page application buck regulator only v out1 = 6v l: mss7341-273mlb input voltage (v) 5 0 supply current (a) 10 30 40 50 100 70 15 25 30 35 3668 g04 20 80 90 60 10 20 40 front page application temperature (c) ?50 ?25 0 supply current (a) 100 1m increased supply current due to catch diode leakage at high temperature front page application catch diode: cmmsh1-60 25 50 75 100 125 150 3668 g05 10 input voltage (v) 5 load current (ma) 600 650 700 20 30 3668 g06 550 500 10 15 25 35 40 450 400 front page application v out1 = 3.3v typical minimum input voltage (v) 5 load current (ma) 600 650 700 20 30 3668 g07 550 500 10 15 25 35 40 450 400 front page application typical minimum load current (ma) 0 ?0.10 load regulation (%) ?0.08 ?0.04 ?0.02 0 0.10 0.04 100 200 250 3668 g08 ?0.06 0.06 0.08 0.02 50 150 300 350 400 front page application referenced from v out1 at 200ma load duty cycle (%) 0 switch current limit (ma) 600 700 80 3668 g09 500 400 20 40 60 100 800 switch peak current limit catch diode valley current limit LT3668 3668f
6 for more information www.linear.com/LT3668 typical p er f or m ance c harac t eris t ics minimum switch on-time/ switch-off time switch v cesat boost pin current minimum input voltage, v out1 = 3.3v minimum input voltage, v out1 = 6v switch current limit switching frequency t a = 25c, unless otherwise noted. transient load response, load step 10ma to 140ma transient load response load step 150ma to 300ma temperature (c) ?50 switch current limit (ma) 700 800 900 25 75 150 3668 g10 600 500 400 ?25 0 50 100 125 0% duty cycle 100% duty cycle catch diode valley current limit temperature (c) ?50 frequency (mhz) 1.2 1.8 2.0 150 3668 g11 1.0 0.8 0 0 50 100 ?25 25 75 125 0.4 2.4 2.2 1.6 1.4 0.6 0.2 r t = 37.4k r t = 95.3k r t = 487k temperature (c) ?50 0 switch on-time/switch off-time (ns) 20 60 80 100 200 140 0 50 75 3668 g12 40 160 180 120 ?25 25 100 125 150 minimum off-time minimum on-time load current = 200ma switch current (ma) 0 switch v cesat (mv) 400 500 600 300 500 3668 g13 300 200 100 200 400 600 700 100 0 t j = ?50c t j = 25c t j = 125c t j = 150c switch current (ma) 0 2 boost pin current (ma) 4 8 10 12 400 20 3668 g14 6 200 100 500 300 600 14 16 18 t a = 150c t a = 25c t a = ?50c load current i out1 (ma) 0 input voltage v in1 (v) 4.0 4.5 5.0 150 250 400 3668 g15 3.5 3.0 3.5 50 100 200 300 350 to start to run front page application v en = v in1 , v out1 = 3.3v load current i out1 (ma) 0 input voltage v in1 (v) 6.5 7.0 7.5 150 250 400 3668 g16 6.0 5.5 5.0 50 100 200 300 350 to start to run front page application v en = v in1 , v out1 = 6v 3668 g17 100s/div v out1 100mv/div i l 100ma/div front page application 3668 g18 100s/div v out1 100mv/div i l 150ma/div front page application LT3668 3668f
7 for more information www.linear.com/LT3668 typical p er f or m ance c harac t eris t ics switching waveforms, burst mode operation switching waveforms, full frequency continuous operation en threshold en pin current ldos: typical dropout voltage ldos: tracking ldos: tracking error ldos: tracking error ldos: guaranteed dropout voltage t a = 25c, unless otherwise noted. en pin voltage (v) 0 en pin current (a) 0.6 0.8 1.0 15 25 40 3668 g22 0.4 0.2 0 5 10 20 30 35 3668 g19 1s/div v sw 5v/div v out1 5mv/div i l 100ma/div i load = 10ma front page application, v out1 = 5v 3668 g20 1s/div v sw 5v/div v out1 5mv/div i l 200ma/div i load = 400ma, front page application temperature (c) ?50 0 threshold voltage (v) 0.1 0.3 0.4 0.5 1.0 0.7 0 50 75 3668 g21 0.2 0.8 0.9 0.6 ?25 25 100 125 150 output current (ma) 0 dropout voltage (mv) 300 400 500 600 160 3668 g26 200 100 250 350 450 550 150 50 0 40 80 120 20 180 60 100 140 200 t a = ?50c t a = 25c t a = 125c t a = 150c output current (ma) 0 dropout voltage (mv) 400 500 600 180160 3668 g27 300 200 0 40 80 120 20 200 60 100 140 100 800 t j = 125c t j = 25c 700 = test points adj2/3 voltage (v) 0 out2/3 voltage (v) 8 9 10 v in2/3 = 11v 5 7 10 3668 g23 7 6 5 4 3 2 1 0 1 2 3 4 6 8 9 temperature (c) 50 v out2/3 -v adj2/3 (mv) 8 9 10 v in2/3 = 6v v adj2/3 = 5v 50 75 150 3668 g24 7 6 5 4 3 2 1 0 ?25 0 25 100 125 v adj2/3 (v) 1 v out2/3 -v adj2/3 (mv) 3 4 6 7 10 3668 g25 2 1 0 ?1 2 43 5 8 9 LT3668 3668f
8 for more information www.linear.com/LT3668 typical p er f or m ance c harac t eris t ics adj2, adj3 pin bias current ldos: internal current limit ldos: internal current limit ldos: reverse output current ldos: reverse output current ldos: input ripple rejection t a = 25c, unless otherwise noted. temperature (c) ?50 adj2/3 pin bias current (na) 300 350 400 25 75 150 3668 g31 250 200 150 100 ?25 0 50 100 125 v adj2/3 = 5v input/output differential (v) 0 0 current limit (ma) 50 150 200 250 350 5 25 35 3668 g32 100 300 20 45 10 15 30 40 t a = 140c t a = 125c t a = 25c t a = ?50c output voltage (v) 0 200 current limit (ma) 225 250 275 325 5 25 35 3668 g33 300 20 45 10 15 30 40 t a = 140c t a = 125c t a = 25c t a = ?50c v in2/3 -v out2/3(nominal) = 1v voltage (v) 0 0 current (ma) 0.4 1.2 10 20 25 45 3668 g34 0.2 0.8 1.0 0.6 5 15 30 35 40 v in2/3 = 0v i out2/3 i adj2/3 temperature (c) ?50 0 current (a) 5 15 20 25 40 35 0 50 75 150 3668 g35 10 30 ?25 25 100 125 v out2/3 = v adj2/3 = 10v v in2/3 = 0v i adj2/3 i out2/3 frequency (hz) 10 100 input ripple rejection (db) 40 60 80 1k 10k 100k 1m 10m 3668 g36 20 0 100 120 v in1 = 12v i out2/3 = 200ma v out2/3 = 5v v in2/3 = 6v + 50mv rms ripple out2 out3 ldos: in2, in3 quiescent current ldos: 5v quiescent current in2 ldos: 5v quiescent current in3/bd temperature (c) ?50 0 quiescent current (a) 10 20 30 40 0 50 100 150 3668 g28 50 60 in2 ?25 25 75 125 v in2/3 = 6v v en = 0.3v v in2/3 = 6v v en = 12v, v in1 = 0 v out2/3 = 5v i load = 5a in3/bd v in2 (v) 0 0 quiescent current i in2 (a) 20 10 40 50 60 30 35 40 100 3668 g29 30 15 5 20 10 25 45 70 80 90 v in1 = v en = 12v v adj2 = 5v v en2/ilim2 = 0v v en2/ilim2 = 2v v in3/bd (v) 0 0 quiescent current i in3/bd (a) 20 10 40 50 60 100 3668 g30 30 15 5 20 10 25 30 70 80 90 v in1 = v en = 12v v adj3 = 5v v en3/ilim3 = 0v v en3/ilim3 = 2v LT3668 3668f
9 for more information www.linear.com/LT3668 ldos: minimum input voltage ldos: load regulation ldos: output noise spectral density temperature (c) ?50 minimum input voltage (v) 0.6 1.8 2.0 2.2 0 50 75 100 3667 g37 0.2 1.4 1.0 0.4 1.6 0 1.2 0.8 ?25 25 125 150 i l = 200ma v out2/3 = 1.1v v in1 = 5v temperature (c) ?50 ?10 load regulation (mv) ?4 ?5 ?6 ?7 ?8 ?9 ?3 ?2 ?1 0 50 100 150 3668 g38 0 ?25 25 75 125 ?i out2/3 = 1ma to 200ma v out2/3 = 1.1v v in2/3 = 2.2v v in1 = 12v frequency (hz) 10n output noise spectral density (v/hz) 100n 10 1k 10k 1m 100k 3668 g39 1n 100 1 c out2/3 = 10f v in2/3 = 6v v adj2/3 = 5v i out2/3 = 200ma typical p er f or m ance c harac t eris t ics ldos: rms output noise ldos: small signal transfer function ldos: transient response ldos: external current limit, r en/ilim = 1.54k ldos: external current limit, r en/ilim = 6.19k ldos: external current limit, r en/ilim = 31.6k t a = 25c, unless otherwise noted. load current (ma) 20 output noise voltage (v rms ) 40 50 70 80 0.01 1 10 100 3668 g40 0 0.1 60 30 10 c out = 10f f out2/3 = 10hz to 100khz v in2/3 = 6v v adj2/3 = 5v frequency (hz) gain (db) ?20 ?10 10 20 10 1k 10k 100k 1m 3668 g41 ?40 100 0 ?30 ?180 phase () ?90 ?45 45 ?225 0 ?135 c out = 10f f out2/3 = 10hz to 100khz v in2/3 = 6v v adj2/3 = 5v i out2/3 = 200ma i out2/3 = 20ma phase gain 3668 g42 100s/div v out2/3 50mv/div i out2/3 100ma/div i out3/2 = 20ma v out3/2 1mv/div v in2/3 = 6v, v out2/3 = 5v c out2/3 = 10f i out2/3 = 20ma to 200ma temperature (c) ?50 current limit (ma) 190 200 150 3668 g43 180 170 0 50 100 ?25 25 75 125 210 v out2/3 = 5v 185 195 175 205 v in2/3 = 5.6v v in2/3 = 15v v in2/3 = 10v temperature (c) ?50 current limit (ma) 50.0 51.0 150 3668 g44 49.0 48.0 0 50 100 ?25 25 75 125 52.0 v out2/3 = 5v 49.5 50.5 48.5 51.5 v in2/3 = 5.6v v in2/3 = 15v v in2/3 = 10v temperature (c) ?50 9.8 current limit (ma) 9.9 10.0 10.1 10.2 ?2 5 0 25 50 3668 g45 75 100 125 150 v out2/3 = 5v v in2/3 = 5.6v v in2/3 = 15v v in2/3 = 10v LT3668 3668f
10 for more information www.linear.com/LT3668 p in func t ions sw (pin 1): the sw pin is the output of the internal power switch. connect this pin to the inductor, the catch diode and the boost capacitor. boost (pin 2): this pin is used to provide a drive volt - age, higher than the input voltage, to the internal bipolar npn power switch of the switching regulator. connect a capacitor (typically 0.22f) between boost and sw. en (pin 3): the en pin is used to put the LT3668 in shut - down mode . ti e to ground to shut down the LT3668. tie to 1 v or more for normal operation. if the en pin is to be pulled below ground, use a series resistor to limit the pin current to 1ma. rt (pin 4): oscillator resistor input. connect a resistor from this pin to ground to set the switching frequency. out3 (pin 6), out2 (pin 10): these are the outputs of the two ldos. stability requirements demand a minimum 10f ceramic output capacitor to prevent oscillations. adj3 (pin 9), adj2 (pin 7): the two ldos of the LT3668 regulate their outputs to follow the voltages at the adj2 and adj3 pins. connect the reference voltage to these pins. fb1 (pin 8): the switching regulator of the LT3668 regu- lates the fb1 pin to 1.2 v. connect the feedback resistor divider tap to this pin. in 2 (pin 11), in3/bd (pin 5): these pins are the inputs of the two ldos. in3/bd also connects to the anode of the internal boost diode and also supplies current to the LT3668s internal regulator when in3/bd is above 3.2v. en2/ilim2 (pin 12), en3/ilim3 (pin 13): precision cur - rent limit programming pins. they connect to collectors of current mirror pnps which are 1/799th the size of the output power pnps of the two ldos. these pins are also the inputs to the current limit amplifiers. current limit thresholds are set by connecting resistors between the en2/ilim2 pin and gnd and between the en3/ilim3 pin and gnd. stability requirements demand 47nf capacitors in parallel to these resistors. for detailed information on how to set the pin resistor values, see the operation section. if any of these pins is not used, tie it to gnd. to disable an ldo, pull its en/ilim pin above 1.2 v. if an en/ilim pin is used as a digital input for enable/disable, ensure rise and fall times of less than 1s. pg ( pin 14): the pg pin is the open-drain output of an internal window comparator. pg remains low until the fb1 pin is within 10% of its final regulation voltage. pg output is valid when v in1 or v in2 are above the minimum input voltage and en is high. in1 (pin 15): the in1 pin supplies current to the internal regulator and to the internal power switch. this pin must be locally bypassed. da (pin 16): connect the anode of the catch diode (d1 in block diagram) to this pin. internal circuitry senses the current through the catch diode providing frequency foldback in overload conditions. gnd ( exposed pad pin 17): this is the ground of all internal circuitry, as well as the power ground used by the catch diode ( d1). the exposed pad must be soldered to the pcb. LT3668 3668f
11 for more information www.linear.com/LT3668 b lock diagra m error amplifier out3 en3/ ilim3 1v 0.4v 0.4v 80 80 1v ldo disable ldo disable out2 pg in2 adj2 adj3 v out2 c4 v in1 c1 c5 v out3 error amplifier current limit amplifier current limit amplifier + ? ldo driver + ? error amplifier + ? ? + 10 9 7 in3/ bd 5 11 en2/ ilim2 12 14 6 b00st 2 sw 3668 bd 1 da 16 13 + ? + ? ? + ldo driver internal ref slope comp burst mode detect oscillator 250khz to 2.2mhz 1.2v in1 15 en 1.32v vc r t 4 rt 1.08v + ? + ? 3 r s q boost diode catch diode current limit c2 v out1 c3 l1 d1 + ? 8 fb1 r2 r1 17 gnd LT3668 3668f
12 for more information www.linear.com/LT3668 o pera t ion the LT3668 combines a 400 ma buck switching regulator and two 200 ma low dropout linear tracking regulators. operation is best understood by referring to the block diagram. the buck regulator part is a constant frequency, current mode step-down regulator. an oscillator, with frequency set by r t , sets an rs flip-flop, turning on the internal power switch. an amplifier and comparator monitor the current flowing between the in1 and sw pins, turning the switch off when this current reaches a level determined by the voltage at vc. an error amplifier measures the output voltage through an external resistor divider tied to the fb1 pin and servos the vc node. if the error amplifiers output increases, more current is delivered to the output; if it decreases, less current is delivered. another comparator monitors the current flowing through the catch diode and reduces the operating frequency when the current exceeds the 500 ma bottom current limit. this foldback in frequency helps to control the output current in fault conditions such as a shorted output with high input voltage. maximum deliverable current to the output is therefore limited by both switch current limit and catch diode current limit. an internal regulator provides power to the control cir- cuitr y. the bias regulator normally draws power from the in1 pin, but if the in3/bd pin is connected to an external voltage higher than 3.2 v, bias power will be drawn from the external source (typically the regulated output voltage). this improves efficiency. the switch driver operates from either in1 or from the boost pin. an external capacitor is used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to fully saturate the internal npn power switch for efficient operation. to further optimize efficiency, the LT3668 automatically switches to burst mode operation in light load situations. between bursts, all circuitry associated with control - ling the output switch is shut down, reducing the input supply current to 50a ( including the current drawn by the ldos). the switching regulator has an overvoltage protection feature which disables switching action when in1 goes above 42v ( typical) during transients. it can then safely sustain transient input voltages up to 60v. the ldo blocks are micropower, low noise 200 ma linear tracking regulators with low dropout voltage and current limit, which provide fast transient response with minimum low esr 10f ceramic output capacitors. the output volt- age of each ldo follows a reference voltage applied to its adjust input with high accuracy. each output current limit can be programmed individually with a single resistor, and pulling the en2/ilim2 or en3/ilim3 pin high shuts down the corresponding ldo. internal protection circuitry includes reverse- battery protection, reverse output protection, reverse-current protection and current limit with foldback. the internal reference voltage circuitry is supplied by the in1 and in2 pins. this allows the ldo at in2 to run independently and supply the switching regulator with its output out2. the en pin is used to place the LT3668 in shutdown, thereby reducing the input current to less than 1a. the LT3668 contains a power good window comparator that indicates whether the output voltage of the switching regulator is within 10% of its nominal value. the output pg of this comparator is an open-drain transistor which is off when the output is in regulation, allowing external resistors to pull the pg pin high. power good is valid if the LT3668 is enabled and in1 or in2 are above their minimum input voltages. internal thermal limiting protects the LT3668 during overload conditions. LT3668 3668f
13 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion s witching r egulator fb1 resistor network the switching regulator output voltage of the LT3668 is programmed with a resistor divider between the output of the switching regulator and the fb1 pin. choose the resistor values according to: r1 = r2 v out1 1.2v C 1 ? ? ? ? ? ? reference designators refer to the block diagram of the LT3668 . 1% resistors are recommended to maintain output voltage accuracy. note that choosing larger resistors will decrease the quiescent current of the application circuit. setting the switching frequency the LT3668 regulators use a constant frequency pwm architecture that can be programmed to switch from 250khz to 2.2 mhz by using a resistor tied from the rt pin to ground. table 1 shows the necessary r t value for a desired switching frequency. table 1: switching frequency vs r t value switching frequency (mhz) r t value (k) 0.25 475 0.3 383 0.4 274 0.5 215 0.6 174 0.8 124 1 95.3 1.2 75 1.4 61.9 1.6 51.1 1.8 43.2 2 37.4 2.2 32.4 operating frequency trade-offs selection of the operating frequency is a trade-off between efficiency, component size, minimum dropout voltage, and maximum input voltage. the advantage of high frequency operation is that smaller inductor and capacitor values may be used. the disadvantages are lower efficiency, lower maximum input voltage, and higher dropout voltage. the highest acceptable switching frequency (f sw(max) ) for a given application can be calculated as follows: f sw(max) = v out1 + v d t on(min) v in1 C v sw + v d ( ) where v in1 is the typical input voltage, v out1 is the output voltage, v d is the catch diode drop (~0.5 v) and v sw is the internal switch drop (~0.5 v at max load). this equation shows that slower switching frequency is necessary to accommodate high v in1 /v out1 ratio. lower frequency also allows a lower dropout voltage. input voltage range depends on the switching frequency because the LT3668 switch has finite minimum on and off times. the switch can turn on for a minimum of ~150 ns and turn off for a minimum of ~190ns ( note that the minimum on- time is a strong function of temperature). the minimum and maximum duty cycles that can be achieved taking minimum on and off times into account are: dc min = f sw ? t on(min) dc max = 1 ? f sw ? t off(min) where f sw is the switching frequency, t on(min) is the minimum switch on-time (~150 ns), and t off(min) is the minimum switch off- time (~190 ns). these equations show that the duty cycle range increases when the switching frequency is decreased. a good choice of switching frequency should allow an adequate input voltage range ( see input voltage range section) and keep the inductor and capacitor values small. LT3668 3668f
14 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion input voltage range the minimum input voltage is determined by either the LT3668s minimum operating voltage of 4.3 v or by its maximum duty cycle ( as discussed in the previous sec - tion). the minimum input voltage due to duty cycle is: v in1(min) = v out1 + v d 1C f sw ? t off(min) C v d + v sw where v in(min) is the minimum input voltage, v out1 is the output voltage, v d is the catch diode drop (~0.5 v), v sw is the internal switch drop (~0.5 v at maximum load), f sw is the switching frequency, and t off(min) is the minimum switch off-time (~190 ns). note that a higher switching frequency will increase the minimum input voltage. if a lower dropout voltage is desired, a lower switching fre - quency should be used. the highest allowed v in1 during normal operation (v in1(op - max) ) is limited by minimum duty cycle and is given by: v in1(op-max) = v out1 + v d f sw ? t on(min) C v d + v sw where v out1 is the output voltage, v d is the catch diode drop (~0.5 v), v sw is the internal switch drop (~0.5 v at maximum load), f sw is the switching frequency, and t on(min) is the minimum switch on-time (~150ns). however, the LT3668 will tolerate inputs up to the absolute maximum ratings of the v in1 and boost pins, regardless of the chosen switching frequency. during such transients where v in1 is higher than v in1(op-max) , the part will skip pulses to maintain output regulation. the output voltage ripple and inductor current ripple will be higher than in normal operation. input voltage transients of up to 60 v are also safely withstood, though the LT3668 stops switching while v in1 > v ovlo ( overvoltage lockout, 42 v typical), al- lowing the output to fall out of regulation. during start - up, short - circuit, or other overload conditions the inductor peak current might reach and even exceed the maximum current limit of the LT3668, especially in those cases where the switch already operates at minimum on- time. the catch diode current limit circuitry prevents the switch from turning on again if the inductor valley current is above 500 ma nominal. inductor selection and maximum output current for a given input and output voltage, the inductor value and switching frequency will determine the ripple current, which increases with higher v in1 or v out1 and decreases with higher inductance and higher switching frequency. a good first choice for the inductor value is: l = v out1 + v d ( ) ? 2.4 f sw where f sw is the switching frequency in mhz, v out1 is the output voltage, v d is the catch diode drop (~0.5 v) and l is the inductor value in h . the inductor s rms current rating must be greater than the maximum load current and its saturation current should be about 30% higher. for robust operation in fault conditions ( start-up or short-circuit) and high input voltage (>30 v), the saturation current should be above 900ma. to keep the efficiency high, the series resistance ( dcr) should be less than 0.3, and the core material should be intended for high frequency applica - tions. table 2 lists several vendors. table 2. inductor vendors vendor url coilcraft www.coilcraft.com sumida www.sumida.com toko www.tokoam.com wrth elektronik www.we-online.com coiltronics www.cooperet.com murata www.murata.com LT3668 3668f
15 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion this simple design guide will not always result in the optimum inductor selection for a given application. as a general rule, lower output voltages and higher switching frequency will require smaller inductor values. if the ap - plication requires less than 400 ma load current, then a lesser inductor value may be acceptable. this allows the use of a physically smaller inductor, or one with a lower dcr resulting in higher efficiency. however, the inductance should in general not be smaller than 10h. be aware that if the inductance differs from the simple rule above, then the maximum load current will depend on input voltage. in addition, low inductance may result in discontinuous mode operation, which further reduces maximum load current. for details of maximum output current and discontinuous mode operation, see linear technologys application note 44. finally, for duty cycles greater than 50% (v out1 /v in1 > 0.5), a minimum inductance is required to avoid sub-harmonic oscillations: l min = v out1 + v d ( ) ? 2 f sw where f sw is the switching frequency in mhz, v out1 is the output voltage, v d is the catch diode drop (~0.5v) and l min is the inductor value in h. catch diode the catch diode ( d 1 from block diagram) conducts current only during switch off-time. use a 1a schottky diode for best performance. peak reverse voltage is equal to v in1 if it is below the overvoltage protection threshold. this feature keeps the switch off for v in1 > ovlo (44 v maximum). for inputs up to the maximum operating voltage of 40 v, use a diode with a reverse voltage rating greater than the input voltage. if transients at the input of up to 60 v are expected, use a diode with a reverse voltage rating only higher than the maximum ovlo of 44 v. if operating at high ambient temperatures, consider using a schottky with low reverse leakage. for example, diodes inc. sbr1u40lp or dfls160, on semi mbrm140, and central semiconductor cmmsh1-60 are good choices for the catch diode. input capacitor bypass the input of the LT3668 circuit with a ceramic capacitor of x7r or x5r type. y5v types have poor performance over temperature and applied voltage, and should not be used. a 1 f to 4.7 f ceramic capacitor is adequate to bypass the LT3668 and will easily handle the ripple current. note that a larger input capacitance is required when a lower switching frequency is used (due to longer on-times). if the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. this can be provided with a low performance electrolytic capacitor. step-down regulators draw current from the input supply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the LT3668 and to force this very high frequency switching current into a tight local loop, minimizing emi. a 1 f capacitor is capable of this task, but only if it is placed close to the LT3668 ( see the pcb layout section). a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the LT3668. a ceramic input capacitor combined with trace or cable inductance forms a high quality ( under damped) tank circuit. if the LT3668 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT3668s voltage rating. this situation is easily avoided ( see the hot plugging safely section). output capacitor and output ripple the output capacitor has two essential functions. along with the inductor, it filters the square wave generated by the LT3668 to produce the dc output. in this role it determines the output ripple, and low impedance at the switching frequency is important. the second function is to store energy in order to satisfy transient loads and stabilize the switching regulators control loop. ceramic capacitors have very low equivalent series resistance (esr) and provide the best ripple performance. a good starting value is: c out1 = 50 v out1 ? f sw LT3668 3668f
16 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion figure 1. burst mode operation where f sw is in mhz, and c out1 is the recommended output capacitance in f. use x5r or x7r types. this choice will provide low output ripple and good transient response. transient performance can be improved with a higher value capacitor if combined with a phase lead capacitor (typically 22pf) between the output and pin fb1. note that a larger phase lead capacitor should be used with a large output capacitor. a lower value of output capacitor can be used to save space and cost but transient performance will suffer. when choosing a capacitor, look carefully through the data sheet to find out what the actual capacitance is under operating conditions ( applied voltage and temperature). a physically larger capacitor, or one with a higher voltage rating, may be required. table 3 lists several capacitor vendors. table 3: capacitor vendors vendor url panasonic www.panasonic.com kemet www.kemet.com sanyo www.sanyovideo.com murata www.murata.com avx www.avxcorp.com taiyo yuden www.taiyo-yuden.com audible noise ceramic capacitors are small, robust and have very low esr. however, ceramic capacitors can sometimes cause problems when used with the LT3668 due to their piezoelectric nature. when in burst mode operation, the LT3668 s switching frequency depends on the load current, and at very light loads the LT3668 can excite the ceramic capacitor at audio frequencies, generating audible noise. since the LT3668 operates at a lower current limit during burst mode operation, the noise is typically very quiet. if this is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. low ripple burst mode operation to enhance efficiency at light loads, the LT3668 oper - ates in low ripple burst mode operation which keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. during burst mode operation, the LT3668 delivers single cycle bursts of current to the output capacitor followed by sleep periods where the output power is delivered to the load by the output capacitor. because the LT3668 delivers power to the output with single, low current pulses, the output ripple is kept below 5 mv for a typical application. as the load current decreases towards a no load condition, the percentage of time that the LT3668 operates in sleep mode increases and the average input current is greatly reduced resulting in high efficiency even at very low loads. note that during burst mode operation, the switching frequency will be lower than the programmed switching frequency. at higher output loads ( above ~50 ma for the front page application) the LT3668 will be running at the frequency programmed by the r t resistor, and will be operating in standard pwm mode. the transition between pwm and low ripple burst mode operation is seamless, and will not disturb the output voltage. 3668 f01 1s/div front page application, v out1 = 5v v sw 5v/div v out1 5mv/div i l 100ma/div i load = 10ma LT3668 3668f
17 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion boost and in3/bd pin considerations capacitor c 2 and the internal boost schottky diode ( see the block diagram) are used to generate a boost voltage that is higher than the input voltage. in most cases a 0.22f capacitor will work well. figure 2 shows two ways to ar - range the boost circuit. the boost pin must be more than 1.9v above the sw pin for best efficiency. for outputs of 2.2v and above, the standard circuit (figure 2 a) is best. for outputs between 2.2 v and 2.5 v, use a 0.47 f boost capacitor. for output voltages below 2.2 v, the boost diode can be tied to the input (figure 2 b), or to another external supply greater than 2.2 v. however, the circuit in figure 2a is more efficient because the boost pin current and in3/bd pin quiescent current come from a lower voltage source. also, be sure that the maximum voltage ratings of the boost and in3/bd pins are not exceeded. the minimum operating voltage of an LT3668 applica - tion is limited by the minimum input voltage (4.3 v) and by the maximum duty cycle as outlined in a previous section. for proper start-up, the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, the boost capacitor may not be fully charged. because the boost capacitor is charged with the energy stored in the inductor, the circuit relies on some minimum load current to get the boost circuit running properly. this minimum load depends on input and output voltages, and on the arrangement of the boost circuit. the minimum load generally goes to zero once the circuit has started. figure?3 shows a plot of minimum load to start and to run as a function of input voltage. in many cases the discharged output capacitor will present a load to the switcher, which will allow it to start. the plots show the worst-case situation where v in1 is ramping very slowly. for lower start-up voltage, the boost diode can be tied to v in1 ; however, this restricts the input range to one-half of the absolute maximum rating of the boost pin. figure 2. two circuits for generating the boost voltage in3/bd LT3668 (2a) for v out1 2.2v boost in1 v in1 c2 d1 v out1 sw da gnd in3/bd LT3668 (2b) for v out1 < 2.2v; v in1 < 25v boost in1 v in1 c2 3668 f02 v out1 sw gnd d1 da figure 3. the minimum input voltage depends on output voltage , load current and boost circuit load current i out1 (ma) 0 input voltage v in1 (v) 4.0 4.5 5.0 150 250 400 3668 f03a 3.5 3.0 3.5 50 100 200 300 350 to start to run front page application v en = v in1 , v out1 = 3.3v load current i out1 (ma) 0 input voltage v in1 (v) 6.5 7.0 7.5 150 250 400 3668 f03b 6.0 5.5 5.0 50 100 200 300 350 to start to run front page application v en = v in1 , v out1 = 6v LT3668 3668f
18 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion shorted and reversed input protection if the inductor is chosen so that it wont saturate exces- sively, the switching regulator will tolerate a shorted output. there is another situation to consider in systems where the output will be held high when the input to the LT3668 is absent. this may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode ored with the switching regulators output. if the in1 pin is allowed to float and the en pin is held high ( either by a logic signal or because it is tied to in1), then the LT3668s internal circuitry will pull its quiescent current through the sw pin. this is fine if the system can tolerate a few a in this state. if the en pin is grounded, the sw pin current will drop to 0.7a. however, if the in1 pin is grounded while the output is held high, regardless of en, parasitic diodes inside the LT3668 can pull current from the output through the sw pin and the in1 pin. figure 4 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. ldos adjustment inputs each ldo output voltage of the LT3668 follows the voltage at the corresponding adjustment pin adj2/adj3. each adjustment pin is pulled down by an internal current source (typically 200 na at 25 c). this current must be taken into consideration if an adjustment pin is to be driven by a high impedance resistive divider. even if the voltage at adj2/adj3 is below the minimum input voltage, the corresponding output will always be regulated to a voltage equal or below the voltage at adj2/adj3. any noise present at an adjustment pin is transferred to the corresponding output, in particular low frequency noise. see the ldo transfer function in the typical performance characteristics section. reference voltage noise can be reduced by connecting a capacitor from adj2/adj3 to ground. however, if the reference voltage is derived from the resistive divider of the switching regulator as shown in the application on page 1, no such bypass capacitor is allowed as it would impair the switching regulator's stability. figure 4. diode d1 prevents a shorted input from discharging a backup battery tied to the output. it also protects the circuit from a reversed input, in which case the resistor at the en pin limits the current drawn from that pin. the LT3668 runs only when the input is present in3/bd LT3668 boost in1 en v in v out backup 3668 f04 sw da d1 mbrs140 fb1 gnd + LT3668 3668f
19 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion input capacitance and stability each ldo is stable with an input capacitor typically between 1f and 10 f. this input capacitor must be placed as close as possible to the corresponding input pin. applications operating with smaller input to output differential voltages and that experience large load transients may require a higher input capacitor value to prevent input voltage droop and letting the regulator enter dropout. very low esr ceramic capacitors may be used. however, in cases where long wires connect the power supply to the ldos input and ground, use of low value input capaci - tors may result in instability. the resonant lc tank circuit formed by the wire inductance and the input capacitor is the cause and not a result of ldo instability. the minimum input capacitance needed to stabilize the application also varies with power supply output imped - ance variations . placing additional capacitance on an ldo s output also helps. however, this requires an order of magnitude more capacitance in comparison with additional input bypassing. series resistance between the supply and an ldos input also helps stabilize the application; as little as 0.1 to 0.5 suffices. this impedance dampens the lc tank circuit at the expense of dropout voltage. a better alternative is to use higher esr tantalum or electrolytic capacitors at the input in place of ceramic capacitors. output capacitance, transient response, stability each LT3668s ldo is stable with a wide range of output capacitors. the esr of the output capacitor affects stabil - ity, most notably with small capacitors. use a minimum output capacitor of 10 f to prevent oscillations. the esr of the output capacitor must not exceed 3. the LT3668 is a micropower device and output load transient response is a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes, especially for low output voltages. bypass capacitors, used to decouple individual components powered by the LT3668, increase the effec - tive output capacitor value. for applications with large load current transients, a low esr ceramic capacitor in parallel with a bulk tantalum capacitor often provides an optimally damped response. note that some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. for a ceramic capacitor, the stress is induced by vibrations in the system or thermal transients. the resulting voltages produced cause appreciable amounts of noise. a ceramic capacitor produced the trace in figure 5 in response to light tapping from a pencil. similar vibration induced behavior can masquerade as increased output voltage noise. figure 5. noise resulting from tapping on a ceramic capacitor v out2 1mv/div 3668 f05 2ms/div v out2 = 5v c out2 = 10f LT3668 3668f
20 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion external programmable current limit, enable each en/ilim pin ( en2/ilim2 and en3/ilim3) is the col- lector of a pnp which mirrors the corresponding ldos output at a ratio of 1:799 (see block diagram). the en2/ ilim2 and en3/ilim3 pins are also the inputs to preci - sion current limit amplifiers. if an output load increases to the point where it causes the corresponding current limit amplifier input voltage to reach 0.4 v, the current limit amplifier takes control of output regulation so that its input clamps at 0.4 v, regardless of the output voltage. the current limit threshold (i limit ) of an ldo is set by attaching a resistor (r imax ) from the corresponding en/ ilim pin to ground: r imax = 799 ? 0.4v i lim C 80 ? in order to maintain stability, each en/ilim pin requires a 47nf capacitor from that pin to ground. in cases where the input to output voltage differential exceeds 10 v, foldback current limit will lower the inter - nal current level limit, possibly causing it to preempt the external programmable current limit. see the internal current limit vs input/output differential graph in the typical performance characteristics section. if an external current limit is not needed, the correspond - ing en /ilim pin must be connected to ground, in which case no capacitor is required. each ldo can be individually shut down by pulling its en/ ilim pin above 1.2 v (1 v typical). note that in this case this pin will draw up to 500 a in certain operating conditions until the ldo is shut down, which the circuit driving this pin must be able to deliver. when an en/ilim pin is only used to enable/disable an ldo, no capacitor is required on this pin. overload recovery each ldo of the LT3668 has a safe operating area pro - tection, which decreases current limit as input-to-output voltage increases, and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. each ldo provides some output current at all values of input-to-output voltage up to the device break- down. when power is first applied to an ldo, the input voltage rises and the output follows the input; allowing the regulator to start- up into very heavy loads. during start- up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. with a high input voltage, a problem can occur wherein the removal of an output short will not allow the output to recover. the problem occurs with a heavy output load when the input voltage is high and the output voltage is low. common situations are: immediately after the removal of a short-circuit or if an ldo is enabled via its en/ilim pin after the input voltage is already turned on. in such cases, the regulator would have to operate its power device outside its safe operating are ( high voltage and high current) in order to bring up the output voltage. since this is prevented by the safe operating area protec - tion, the output gets stuck at a low voltage. essentially, the load line for such a load intersects the output current curve at two points, resulting in two stable output operating points for the regulator. with this double intersection, the input power supply needs to be cycled down to zero and brought up again to make the output recover. protection features the LT3668 ldos protect against reverse-input voltages, reverse-output voltages and reverse output-to-input volt - ages. current limit protection and thermal overload protec- tion protect the ldos against current overload conditions at their outputs. for normal operation, do not exceed the maximum operating junction temperature. the LT3668 in2 pin withstands reverse voltages of 45 v. the device limits current flow to less than 300a ( typically less than 10a) and no negative voltages appear at out2. the ldos incur no damage if their outputs are pulled below ground. if an input is left open circuit or grounded, the corresponding output can be pulled below ground by 45 v. no current flows through the pass transistor from the output. if the input is powered by a voltage source, the output sources current equal to its current limit capability and the LT3668 protects itself by thermal limiting. note that the externally programmable current limit is less accurate if the output is pulled below ground. LT3668 3668f
21 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion common ceramic capacitor characteristics give extra consideration to the use of ceramic capacitors. manufacturers make ceramic capacitors with a variety of dielectrics, each with different behavior across tempera - ture and applied voltage. the most common dielectrics are specified with eia temperature characteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics provide high c-v products in a small package at low cost, but exhibit strong voltage and temperature coefficients, as can be seen for y5v in figures 6 and 7. when used with a 5 v regulator, a 16v 10 f y5v capacitor can exhibit an effective value as low as 1 f to 2 f for the dc bias voltage applied, and over the operating temperature range. the x5r and x7r dielectrics yield much more stable charac - teristics and are more suitable for use as input and output capacitors. the x7r type works over a wider temperature range and has better temperature stability, while the x5r is less expensive and is available in higher values. still exercise care when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be significant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. figure 6. ceramic capacitor dc bias characteristics figure 7. ceramic capacitor temperature characteristics dc bias voltage (v) change in value (%) 3668 f06 20 0 ?20 ?40 ?60 ?80 ?100 0 4 8 10 2 6 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f temperature (c) ?50 40 20 0 ?20 ?40 ?60 ?80 ?100 25 75 3668 f07 ?25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f LT3668 3668f
22 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. figure 8 shows the recommended component placement with trace, ground plane and via locations. note that large, switched currents flow in the LT3668s in1, sw, gnd and da pins, the catch diode and the input capacitor. the loop formed by these components should be as small as possible. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local, unbroken ground plane below these components. the sw and boost nodes should be as small as possible. keep the fb1 node small so that the ground traces will shield it from the sw and boost nodes. the exposed pad must be soldered such that it can act as a heat sink . (see high temperature considerations section.) hot plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitors of LT3668 circuits. however, these ca - pacitors can cause problems if the LT3668 is plugged into a live supply. the low loss ceramic capacitor, combined with stray inductance in series with the power source, forms an under damped tank circuit, and the voltage at the input pins of the LT3668 can ring to twice their nominal input voltage, possibly exceeding the LT3668s rating and damaging the part. if the input supply is poorly controlled or the user will be plugging the LT3668 into an energized supply, the input network should be designed to prevent this overshoot. see linear technology application note?88 for a complete discussion. high temperature considerations the LT3668s maximum rated junction temperature of 125c limits its power handling capability. power dissipation within the switching regulator can be estimated by calculating the total power loss from an efficiency measurement and subtracting inductor loss. be aware that at high ambient temperatures the external schottky diode will have significant leakage current ( see typical performance characteristics), increasing the qui- escent current of the switching regulator. the power dissipation of each ldo is comprised of two components. each power device dissipates: p pass = (v in ? v out ) ? i out where p pass is the power, v in the input voltage, v out the output voltage, and i out the output current. the base currents of the ldo power pnp transistors flow to ground internally and are the major component of the ground current. for each ldo, this causes a power dissipation p gnd of: p gnd = v in ? i gnd where v in is the input voltage and i gnd the ground current generated by the corresponding power device. gnd pin current is determined by the current gain of the power figure 8. good pcb layout ensures proper, low emi operation 1 16 sw in1 gnd out1 15 14 13 12 11 10 9 vias to local ground plane 2 3 4 5 6 7 8 LT3668 3668f
23 for more information www.linear.com/LT3668 a pplica t ions i n f or m a t ion pnp, which has a typical value of 40 for the purpose of this calculation: i gnd = i out 40 the total power dissipation equals the sum of the power loss in the switching regulator and the two ldo compo- nents listed above. the LT3668 has internal thermal limiting that protects the device during overload conditions. if the junction temperature reaches the thermal shutdown threshold, the LT3668 will shut down the ldos and stop switching to prevent internal damage due to overheating. for continuous normal conditions, do not exceed the maximum operat - ing junction temperature. carefully consider all sources of thermal resistance from junction-to-ambient including other nearby heat sources. the LT3668 package has an exposed pad that must be soldered to a ground plane to act as heat sink. to keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the LT3668 to additional ground planes within the circuit board and on the bottom side. the die temperature rise is calculated by multiplying the power dissipation of the LT3668 by the thermal resistance from junction to ambient. example: given the front page application with maximum output current, an input voltage of 12 v and a maximum ambient temperature of 85 c, what will the maximum junction temperature be? as can be seen from the typical performance characteris- tics, the switching regulator efficiency approaches 85% at 400ma output current. this leads to a power loss, p loss , of : p loss = 5v ? 400ma ? 1 0.85 C 1 ? ? ? ? ? ? = 353mw (for the sake of simplicity and as a conservative estimate assume that all of this power is dissipated in the LT3668.) the power dissipations of the ldo power devices are: p pass2 = (5v ? 2.5v) ? 100ma = 250mw p pass3 = (5v ? 3.3v) ? 100ma = 170mw for 100 ma load current a maximum ground current of 2.5ma is to be expected. thus, the corresponding power dissipations are: p gnd2 = p gnd3 = 5v ? 2.5ma = 12.5mw finally, the total power dissipation is: p tot = p loss + p pass2 + p pass3 + p gnd2 + p gnd3 = 786mw since the msop package has a thermal resistance of ap- proximately 40 c/w, this total power dissipation would raise the junction temperature above ambient by: 0.786 w ? 40c/w = 32c with the assumed maximum ambient temperature of 85 c, this puts the maximum junction temperature at: t jmax = 85c + 32c = 117c other linear technology publications application notes 19, 35 and 44 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. design note 318 shows how to generate a bipolar output supply using a buck regulator. LT3668 3668f
24 for more information www.linear.com/LT3668 6v, 5v and 5v (follower) step-down converter 3668 ta02 en2/ilim2 en3/ilim3 gnd 5v 150ma c4 10f c5 10f in1 LT3668 boost sw da in3/bd in2 on off en pg rt c1 4.7f c2 0.22f c6 22pf l1 27h r1 232k d1 dfls160 6v 100ma r2 931k r3 294k rt 174k f = 600khz v in 7v to 40v transient to 60v 5v 150ma (follows out3) c3 22f fb1 adj2 out2 out3 adj3 c1-c5: x5r or x7r l1: sumida cdrh5d28r/hp typical a pplica t ions LT3668 3668f
25 for more information www.linear.com/LT3668 using digital output of a microcontroller as reference voltage 3668 ta03 en2/ilim2 en3/ilim3 gnd 3.3v, 200ma c4 10f c5 10f c7 47nf in1 LT3668 boost sw da in3/bd in2 fb1 on off en pg rt adj2 out2 out3 adj3 c1 4.7f c2 0.1f d1 dfls160 c6 22pf l1 10h r1 178k 4.05v r2 511k r3 294k rt 37.4k r4 12.7k f = 2mhz v in 7.5v to 16v transient to 60v v dd c i/o 3.3v 25ma off-board supply, for example: sensors c3 10f c1-c5: x5r or x7r l1: sumida cdrh4d22/hp typical a pplica t ions LT3668 3668f
26 for more information www.linear.com/LT3668 typical a pplica t ions three matching 5v supplies programming ldo current limits with a digital/analog converter 3.01k 3.01k v dac dac output 0v to 0.8v 47nf en2/ilim2 LT3668 current limit = 799 0.8v ? v dac 3.01k + 160 1.5k i dac dac output 0a to 267a 47nf 3668 ta05 en2/ilim2 LT3668 current limit = 799 0.4v ? i dac ? 1.5k 1.5k + 80 3668 ta04 en2/ilim2 en3/ilim3 gnd 5v 100ma* c4 10f c5 10f c9 47nf in1 LT3668 boost in3/bd in2 sw da adj2 fb1 en rt out2 out3 adj3 c2 0.22f d1 dfls160 c8 22pf l1 22h r1 931k r2 294k rt 174k r3 3.09k c10 47nf r4 3.09k f = 600khz v in 6v to 25v* 5v 100ma* c3 22f 5v 400ma c1-c5: x5r or x7r l1: sumida cdrh4d22/hp * 100ma current limit. derate output current at higher ambient temperatures and input voltages to maintain junction temperature below the absolute maximum c7 1f c6 1f c1 2.2f LT3668 3668f
27 for more information www.linear.com/LT3668 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (mse16) 0213 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev f) LT3668 3668f
28 for more information www.linear.com/LT3668 ? linear technology corporation 2014 lt 1014 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LT3668 r ela t e d p ar t s typical a pplica t ion part number description comments lt3667 40v, 400ma step-down switching regulator with dual fault protected ldos v in : 4.3v to 40v, v out(min) = 0.8v, i q = 50ma, i sd < 1a, msop-16e, 3mm 5mm qfn-24, lt 3500 36v (40v max ), 2a (i out ), 2.2 mhz step-down switching regulator with ldo controller v in : 3v to 36v, v out(min) = 0.8v, i q = 2.5ma, i sd < 12a, 3mm 3mm dfn-10, msop-16e lt 1939 25v, 2a (i out ), 2.2mhz step-down switching regulator with ldo controller v in : 3v to 25v, v out(min) = 0.8v, i q = 2.5ma, i sd < 12a, 3mm 3mm dfn-10, msop-16e lt 3694 36v (70v max ), 2.6a (i out ), 2.5mhz step-down switching regulator with dual ldo controller v in : 4v to 36v, v out(min) = 0.8v, i q = 1ma, i sd < 1a, 4mm 5mm qfn-28, tssop-20e lt 3507/lt3507a 36v, 2.5mhz, t riple (2.4a + 1.5a + 1.5a (i out ) with ldo controller high efficiency step-down dc/dc converter v in : 4v to 36v, v out(min) = 0.8v, i q = 7ma, i sd = 1a, 5mm 7mm qfn-38 lt 3970 40v, 350ma (i out ), 2.2mhz step-down switching regulator with i q = 2.5a v in : 4.2v to 40v, v out(min) = 1.2v, i q = 2.5a, i sd < 1a, 3mm 2mm dfn, msop-10 lt 3502/lt3502a 40v, 500ma (i out ), 1.1mhz/2.2mhz step-down switching regulator v in : 3v to 40v, v out(min) = 0.8v, i q = 1.5ma, i sd < 1a, 2mm 2mm dfn-8, msop-10e 3668 ta06 en2/ilim2 en3/ilim3 gnd 5v 200ma (fault protected) 5v 200ma (fault protected) c5 10f c4 10f in1 LT3668 boost sw da in3/bd in2 fb1 en pg rt adj2 out2 out3 adj3 c1 4.7f c2 0.22f c6 22pf l1 27h r2 1.18m d1 dfls160 r3 294k r t1 174k f = 600khz v in 7v to 40v c7 4.7f c8 0.47f c9 22f 5v 750ma c3 22f on off on off boost sw bd out v out en/uvlo pg lt3973-5 gnd c1 - c9: x5r or x7r l1: sumida cdrh5d28r/hp rt v in l2 15h r t2 215k f=600khz 5v/0.75a supply with tw o 0.2a tracking outputs LT3668 3668f

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